Information processing devices have been used in a wide range of applications and there is an increasing demand that such devices form advanced computation processes and have capabilities for processing large amounts of data such as still images and moving images at high speeds. As a technique that satisfies such demands, a structure that is provided with a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), or the like that dedicatedly executes particular computations and processes besides a host processor and thereby reduces the load imposed on the processes of the host processor such as a CPU and improves the processing capabilities of information processing device is known.
However, information processing device that have appeared in recent years need to perform compression/decompression processes, computation processes, and so forth based on a variety of standards for multimedia data such as still images, moving images, sound, and music and communication processes that transmit and receive a variety of types of data through a network such as the Internet based on a variety of protocols have been used. In addition, since there is concern about the safety of information transmitted and received over the network, an encryption process that secures information, and a decryption process that restores original information, and so forth are required. Thus, if information processing devices are provided with many DSPs, ASICs, and so forth corresponding to these processes, the circuit scale and cost would become huge.
Thus, a structure in which information processing devices are provided with data processing devices composed of a reconfigurable device such as an FPGA (Field Programmable Gate Array), a CPLD (Complex Programmable Logic Device) or a DRP (Dynamically Reconfigurable Processor) and a program stored in the data processing device that is rewritten and executed when necessary so as to improve the throughput of the information processing device and deal with a variety of processes at low cost has been contemplated.
The reconfigurable device is provided with an internal memory that stores a program (object code), loads an object code stored in an external memory to the internal memory under the control of a CPU or the like, configures an internal circuit corresponding to the loaded object code, and executes a process for data that are input to the circuit.
Details of DRPs are presented, for example, in Patent Literatures 1 to 6 and Non-patent Literature 1. DRPs are structured to have a computation section that executes a computation process and a control section that controls the operation of the computation section. The computation section is provided with a plurality of small-scale computation units and an interconnect section that changes these connections so as to execute a variety of processes by changing instruction codes supplied to the computation units and interconnect section.
DRPs can execute a variety of processes. For example, DRPs may read data from a memory during the execution of a process and then continue the process using such data. Although DRPs are provided with an internal memory, the storage capacity may be limitedly small. Thus, when DRPs execute a process and refer to a table or data that need a large storage capacity of memory, they need to access the memory that stores them. This processing method is presented, for example, in Patent Literature 7 and Patent Literature 8.
When the foregoing background art data processing device executes a process corresponding to an object code composed of at least one piece of configuration information generated corresponding to data to be processed, the device uses a technique that directly specifies the location of configuration information stored therein and executes the process.
In this context, configuration information is information that is necessary to virtually structure a circuit in a data processing device and that includes computational instructions for computation units at particular time points, information that represents the relationship between the connections of the individual computation units in the interconnect section, information that represents the relationship between event signals and configuration information to be selected next, and so forth. An object code is a set of configuration information that is necessary to execute a desired process.
However, in such a method, if a plurality of object codes are installed in data processing device and storage locations of configuration information of these object code overlap, they need to be synthesized such that they do not overlap.
In addition, if a plurality of object codes or a large scale object code is installed in the data processing device and thereby the number of pieces of configuration information exceeds the maximum value that the data processing device can store, it needs to, for example, stop the operation, replace a stored object code with another one, and restart the operation. To do that, an external processing device such as an MPU is required. However, since the background art data processing device can only install configuration information at a location decided when the object code was synthesized, if configuration information composed of the same functional code needs to be installed at different locations, a plurality of sets of configuration information composed of the same functional code needs to be prepared. In this case, since configuration information cannot be shared, a data processing device needs to store a plurality of sets of same configuration information or a process will occur in which the same configuration information is rewritten, the process of the device becomes slow as a problem of the background art device.
To solve such a problem, the applicant of the present invention has proposed a data processing device that does not restrict storage destinations of configuration information and that allows configuration information to be shared (the data processing device filed as Japanese Patent Application No. 2006-103987, hereinafter referred to as Prior Art Invention 1).
In this Prior Art Invention 1, in addition to the foregoing control section, the data processing device is provided with an auxiliary control section that controls state transitions in a predetermined group whose scale is smaller than that of state transitions that the control section controls such that the control section controls state transitions between the groups and the auxiliary control section controls state transitions in each group. In the structure where control structures are hierarchically formed, since the auxiliary control section can control state transitions more quickly than does the control section, the applicant insists that the prior art data processing device can execute processes at higher speeds than does ordinal data processing device.
However, when object codes are actually generated from applications and the operations of data processing device corresponding to the object codes are verified, the result shows that the control section often controls state transitions depending on applications.
In this case, since the chance in which the control source of state transitions that change from the auxiliary control section to the control section increases and the changing time also increases, the process time of the entire data processing device may become longer than that of the structure that does not have the auxiliary control structure. In other words, the process time of data processing device having a hierarchical control configuration may be longer than that of data processing device having a non-hierarchical control structure.
To solve such a problem, the applicant of the present invention has proposed a data processing device having a structure in which the required operation time is shortened in such a manner that the control section controls state transitions simultaneously with the operation of the computation section (the data processing device filed as Japanese Patent Application No. 2008-215764, hereinafter referred to as Prior Art Invention 2).
However, in Prior Art Invention 2, since the control section cannot control state transitions simultaneously with the operation of the computation section if each state has many branches, the device according to this invention slightly reduces the required operation time. In addition, when the device is provided with the auxiliary control section, the entire control of the data processing device becomes complicated.
Moreover, the applicant of the present invention has proposed a data processing device that uses object codes to which logical numbers and real numbers have been allocated and that causes the state management section to hold the next logical number and the next real number so as to realize a large-scale object code having pieces of configuration information that exceed those that parallel computation device can have without a configuration number converting section (the data processing device filed as Japanese Patent Application No. 2009-019561, hereinafter referred to as Prior Art Invention 3).
However, in Prior Art Invention 3, since logical numbers and real numbers are pre-allocated to object codes, when a process is executed, the location of configuration information is restricted and thereby the performance of the data processing device may deteriorate. In addition, while configuration information is being written, unless all the next logical numbers and the next real numbers have been rewritten in the state management section, the operation of the computation section cannot be resumed. Thus, when configuration information of the transition destination from many states is written, the rewritten overhead of the state management section becomes a problem of this prior art invention.